Research on Optimal Design of Chip ESD Protection Circuit Based on CMOS Technology

Shuyang Liu

doi:10.62051/mxk4dx97

Authors

Shuyang Liu

DOI:

https://doi.org/10.62051/mxk4dx97

Keywords:

CMOS; ESD; Full Chip ESD Protection; Analog to Time Conversion Chip.

Abstract

A high frequency circuit based on ESD protection and a new type of power grounding clamp circuit are designed. The oblique edge interfinger diode is used to achieve the optimal design of layout and performance. The design of electrostatic discharge protection circuit and flowsheet were completed in Jazz0.18-micron silicon germanium BiCMOS process. The protection voltage of electrostatic discharge is 3000 V. Higher electrostatic protection level can be obtained by changing the bifurcation index of diode. Improved protection of up to 4500 volts can be achieved. Through the test of the chip, it is proved that the chip fully meets the design requirements and can realize various types of digital circuits.

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