Analysis of Delay Limitation and Circuit Power Balance Optimisation for CMOS Based Circuits

Ruotong Li

doi:10.62051/505v3198

Authors

Ruotong Li

DOI:

https://doi.org/10.62051/505v3198

Keywords:

Integrated Circuit; Power Consumption; Delay; Gate size; Voltage.

Abstract

As integrated circuits and technology have advanced, people's requirements for integrated circuits are getting higher and higher, and integrated circuits with high performance, low latency and low power consumption characteristics are needed to satisfy all kinds of human needs. However, meeting these needs requires a balanced optimization of circuit delay and energy consumption. The gate size and voltage need to be varied simultaneously, and the most suitable voltage and gate are found by combining the gate size and voltage ratio using a linear programming solver. This method can find the optimal gate size and voltage for minimum power circuits with delay requirements, and it also provides new possibilities for comprehensive optimization of Complementary Metal Oxide Semiconductor (CMOS) integrated circuits from both performance and energy perspectives and provides new ideas for IC optimization. In the future, it is necessary to continue to explore the automatic optimization techniques and use deep learning techniques to obtain more efficient circuit optimization methods.

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References

LAN X Z. Design Methodology for Low-Power CMOS Integrated Circuits. Microelectronics, 2004.

Yin Li, Cao Weigang, Wang Xiaohuan. Application of CMOS integrated circuits. Wireless Internet Technology, 2012 (7): 183-183.

Xu YJ. Power consumption estimation and low-power design of integrated circuits. Ph.D. Thesis, Institute of Computing Technology, Chinese Academy of Sciences, April, 2006.

Ravelo B, Pérennec A, Le Roy M. Application of negative group delay active circuits to reduce the 50% propagation Delay of RC-line model. 2008 12th IEEE Workshop on Signal Propagation on Interconnects. IEEE, 2008: 1-4.

Xu P, Pan Z. The insertion of high-k dielectric materials in multilayer graphene nanoribbon interconnects for reducing propagation delay and expanding bandwidth. Organic Electronics, 2020, 78: 105607.

Hashimoto M, Onodeva H. Increase in delay uncertainty by performance optimization. ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No. 01CH37196). IEEE, 2001, 5: 379-382.

Qian F W. Design on CMOS integrated circuit of low power consumption. Proceedings of the 2018 7th International Conference on Advanced Materials and Computer Science (ICAMCS 2018), Dalian, China. 2018: 21-22.

Visweswariah. Optimization techniques for high-performance digital circuits. 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD). IEEE, 1997: 198-207.

Carlson B S, Lee S J. Delay optimization of digital CMOS VLSI circuits by transistor reordering. IEEE transactions on computer-aided design of integrated circuits and systems, 1995, 14(10): 1183-1192.

Carlson B S, Chen C Y R. Effects of transistor reordering on the performance of MOS digital circuits. [1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems. IEEE, 1992: 121-124.

Muñoz M M, Kessler H, Porto M, et al. Transistor Reordering for Electrical Improvement in CMOS Complex Gates. 2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI). IEEE, 2022: 1-6.

Bansal P, Somwanshi D K, Dhaliwal B S, et al. The roles of delay and power optimization techniques in VLSI design. Advances in Image and Data Processing using VLSI Design, Volume 1: Smart vision systems. Bristol, UK: IOP Publishing, 2021: 4-1-4-21.

Van Ginneken L P P P. Buffer placement in distributed RC-tree networks for minimal Elmore delay. 1990 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 1990: 865-868.

Sreenivasulu P, Khan P K, Rao K S, et al. Power Scaling in CMOS Circuits by Dual Threshold Voltage Technique. International Journal of Engineering and Innovative Technology (IJEIT), 2013, 3(1).

Suguna T, Rani M J. Survey on power optimization techniques for low power VLSI circuit in deep submicron technology. International Journal of VLSI design and Communication Systems, 2018, 9(1): 1-15.

Raut K J, Chitre A V, Deshmukh M S, et al. Low power VLSI design techniques: A review. Journal of University of Shanghai for Science and Technology, 2021, 23(11): 172-183.

Sutherland I, Sproull R F, Harris D. Logical effort: designing fast CMOS circuits. Morgan Kaufmann, 1999.