An Optimized 4-bits Absolute Value Detector
DOI:
https://doi.org/10.62051/0jwh7s16Keywords:
Half-adder, Logic effort, Critical path, Energy optimization.Abstract
The binary absolute value detector is crucial in today's computer domain, especially in computer storage and analysis systems. It ensures the integrity and accuracy of data. Therefore, this paper proposes an optimized design of a 4-bit absolute value detector aimed at finding the circuit with the lowest energy consumption. Firstly, this paper introduces a design different from the traditional absolute value calculator, resulting in a reduced total number of stages in the circuit. Secondly, this paper calculates the delay of the main path can be using the logic effort formula and determine the specific gate sizing value for each logic component. Finally, this paper adjusts sizing and power supply ( ) ratio to achieve the lowest energy consumption at 1.5 times the minimum delay. The detector exhibits fewer critical path gates, resulting in lower average delay compared to traditional designs and features an even number of gates which means it has lower delay fluctuations across different inputs.
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Sridevi N, Jamal K, Mannem K. Implementation of Cyclic Redundancy Check in Data Recovery. 2021 Second International Conference on Electronics and Sustainable Communication Systems (ICESC). IEEE, 2021: 17-24.
Iranmanesh S, Raikos G, Jiang Z, et al. CMOS implementation of a low power absolute value comparator circuit. 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS). IEEE, 2016: 1-4.
Prakash J, Kiran B R, Sathish P. The Efficient Implementation to Optimize Power and Delay Using Data Selector. ICTACT Journal on Microelectronics, 2021: 1159-1165.
Zwillinger D. CRC standard mathematical tables and formulas. Chapman and hall/CRC, 2018.
Lin C C, Lin C S, Tsai Y H, et al. don’t care computation and De Morgan transformation for threshold logic network optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021, 41(5): 1412-1422.
Wang J, Sun J, Sun Q. Single-PPLN-based simultaneous half-adder, half-subtracter, and OR logic gate: proposal and simulation. Optics express, 2007, 15(4): 1690-1699.
Hassanpourghadi M, Zamani M, Sharifkhani M. A low-power low-offset dynamic comparator for analog to digital converters. Microelectronics Journal, 2014, 45(2): 256-262.
Anand S, Ghosh P K, Kumar M, et al. Logical Effort to study and Compare the Performance of VLSI Adders. UACEE International Journal of Advances in Electronics Engineering, 2011, 1: 23-27.
Singh K, Jain A, Mittal A, et al. Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms. Integration, 2018, 60: 25-38.
Li G, Yan J, Chen L, et al. Energy consumption optimization with a delay threshold in cloud-fog cooperation computing. IEEE access, 2019, 7: 159688-159697.
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